Synthesis for Testability by Two-Clock Control

In previous studies clock control has been inserted after design to improve the testability of a sequential circuit. In this paper we propose a two-clock control scheme that is included as a part of the logic synthesis of a finite state machine (fsm). The scheme has low area overhead and competes well with scan methods in its ability to initialize and observe circuit states. The states of the machine are assigned a pair of binary values using a novel split coding system. The purpose of the encoding is to ease navigation between any pair of states using a combination of normal and test-mode transitions. W e require a Hamiltonian cycle to exist in the state transition graph. Our investigation of the f sm benchmark shows that either such a cycle already exists or can be created with the insertion of a small number of transition edges. W e also present synthesis results to show that the area penalty is small.